module comparator2BitProcedure(
    input wire[1:0] a, b,
    output reg eq
);
always @(a,b)    // sensitivity list
                 // block executes iff there are changes in 'a' and/or 'b'
begin
    if (a[0]==b[0] && a[1]==b[1]) 
        eq = 1;
    else
        eq = 0;
end
endmodule