module full_adder(
    input A,
    input B,
    input CIN,
    output reg SUM,
    output reg COUT
    );
    
    reg p, g;  // internal signals
    
    // LHS assignments in always blocks must be declared registers,
    // but that does not mean it always synthesizes to a register in hardware
    always @(A, B, CIN)
        begin
            p = A ^ B;
            g = A & B;
            SUM <= p ^ CIN;
            COUT <= g | (p & CIN);
        end
    
endmodule