// time unit of 1ns with precision of 1ps
`timescale 1ns / 1ps

module test_full_adder(

    );
    
    // declare inputs
    reg A;
    reg B;
    reg CIN;
    
    // declare outputs
    wire SUM;
    wire COUT;
    
    // instantiate device-under-test
    // i.e. object 'dut' of type 'full_adder' with following parameters created.
    full_adder dut(A, B, CIN, SUM, COUT);
    
    // stimuli as part of test
    // initial is only used for testbenches
    initial
        begin
            A = 0; B = 0; CIN = 0; #10;  // # is the delay statement
            A = 0; B = 0; CIN = 1; #10;  // which delays for 10 time units
            A = 0; B = 1; CIN = 0; #10;
            A = 0; B = 1; CIN = 1; #10;
            A = 1; B = 0; CIN = 0; #10;
            A = 1; B = 0; CIN = 1; #10;
            A = 1; B = 1; CIN = 0; #10;
            A = 1; B = 1; CIN = 1; #10;
        end

endmodule