projects:electronics:fpga:xilinx
Xilinx
Mojo Development Board
Installation
Xilinx ISE Webpack
Borrowed the Mojo V3 development board that comes packaged with the ATmega32U4 and Xilinx Spartan-6 FPGA, from Adrian. The latter (Spartan-6) is long discontinued, and its development framework has already reached EOL. Archives of the last updated Xilinx ISE Webpack is still available though, following the instructions below (noting the need for account creation and export declaration form before downloading):
Following the O'Reilly guide to install the ISE Webpack license. After running the ISE (script at /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/ise), use the screenshots below as a guide to obtain a license and load it:
Mojo IDE
The Mojo IDE is a little simpler, with download links supplied on the Alchitry Labs download page. The program runs on Java, so for Ubuntu, install the JRE as well:
sudo apt install default-jre
For serial port access, add current user to dialout group, and copy driver files to rules:
sudo usermod -aG dialout MYUSER sudo cp /usr/local/tools/alchitry-labs-1.2.7/driver/99* /etc/udev/rules.d/
For optional convenience access to the Mojo IDE via run template (Alt-F2), add a symbolic link to /usr/bin:
ln -s /usr/local/tools/alchitry-labs-1.2.7/alchitry-labs /usr/bin/alchitry-labs
Connecting board
[909168.722600] usb 5-1: new full-speed USB device number 16 using xhci_hcd [909168.901383] usb 5-1: New USB device found, idVendor=29dd, idProduct=8001, bcdDevice= 1.00 [909168.901399] usb 5-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [909168.901406] usb 5-1: Product: Mojo V3 [909168.901410] usb 5-1: Manufacturer: Embedded Micro [909168.982432] cdc_acm 5-1:1.0: ttyACM0: USB ACM device [909168.988817] input: Embedded Micro Mojo V3 Mouse as /devices/pci0000:00/0000:00:08.1/0000:05:00.4/usb5/5-1/5-1:1.2/0003:29DD:8001.000A/input/input41 [909168.989057] input: Embedded Micro Mojo V3 Keyboard as /devices/pci0000:00/0000:00:08.1/0000:05:00.4/usb5/5-1/5-1:1.2/0003:29DD:8001.000A/input/input42 [909169.047021] hid-generic 0003:29DD:8001.000A: input,hidraw5: USB HID v1.01 Mouse [Embedded Micro Mojo V3] on usb-0000:05:00.4-1/input2
Build project logs for the default Mojo top level program
****** PlanAhead v14.7 (64-bit)
**** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source /home/justin/Documents/_local/_temp/mojotest/testproject/work/project.tcl
# set projDir "/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead"
# set projName "testproject"
# set topName top
# set device xc6slx9-2tqg144
# if {[file exists "$projDir/$projName"]} { file delete -force "$projDir/$projName" }
# create_project $projName "$projDir/$projName" -part $device
# set_property design_mode RTL [get_filesets sources_1]
# set verilogSources [list "/home/justin/Documents/_local/_temp/mojotest/testproject/work/verilog/mojo_top_0.v" ]
# import_files -fileset [get_filesets sources_1] -force -norecurse $verilogSources
# set ucfSources [list "/usr/local/tools/alchitry-labs-1.2.7/library/components/mojo.ucf" ]
# import_files -fileset [get_filesets constrs_1] -force -norecurse $ucfSources
# set_property -name {steps.bitgen.args.More Options} -value {-g Binary:Yes -g Compress} -objects [get_runs impl_1]
# set_property steps.map.args.mt on [get_runs impl_1]
# set_property steps.map.args.pr b [get_runs impl_1]
# set_property steps.par.args.mt on [get_runs impl_1]
# update_compile_order -fileset sources_1
# launch_runs -runs synth_1
[Mon Dec 12 08:30:32 2022] Launched synth_1...
Run output will be captured here: /home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.runs/synth_1/runme.log
# wait_on_run synth_1
[Mon Dec 12 08:30:32 2022] Waiting for synth_1 to finish...
*** Running xst
with args -ifn mojo_top_0.xst -ofn mojo_top_0.srp -intstyle ise
Reading design: mojo_top_0.prj
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.srcs/sources_1/imports/verilog/mojo_top_0.v" into library work
Parsing module <mojo_top_0>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating module <mojo_top_0>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <mojo_top_0>.
Related source file is "/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.srcs/sources_1/imports/verilog/mojo_top_0.v".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_ss> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_mosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_sck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_tx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_rx_busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit tristate buffer for signal <spi_miso> created at line 26
Found 1-bit tristate buffer for signal <avr_rx> created at line 27
Found 1-bit tristate buffer for signal <spi_channel<3>> created at line 28
Found 1-bit tristate buffer for signal <spi_channel<2>> created at line 28
Found 1-bit tristate buffer for signal <spi_channel<1>> created at line 28
Found 1-bit tristate buffer for signal <spi_channel<0>> created at line 28
Summary:
inferred 6 Tristate(s).
Unit <mojo_top_0> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Tristates : 6
1-bit tristate buffer : 6
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <mojo_top_0> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block mojo_top_0, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -2
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
=========================================================================
[Mon Dec 12 08:30:36 2022] synth_1 finished
# launch_runs -runs impl_1
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design mojo_top_0.ngc ...
WARNING:NetListWriters:298 - No output is written to mojo_top_0.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file mojo_top_0.edif ...
ngc2edif: Total memory usage is 91696 kilobytes
Parsing EDIF File [/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.data/cache/mojo_top_0_ngc_963dc69d.edif]
Finished Parsing EDIF File [/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.data/cache/mojo_top_0_ngc_963dc69d.edif]
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
Parsing UCF File [/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.srcs/constrs_1/imports/components/mojo.ucf]
CRITICAL WARNING: [Constraints 18-11] Could not find net 'clk' [/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.srcs/constrs_1/imports/components/mojo.ucf:3]
Finished Parsing UCF File [/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.srcs/constrs_1/imports/components/mojo.ucf]
CRITICAL WARNING: [Constraints 18-329] No definition for group 'clk', timing constraint is ignored [/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.srcs/constrs_1/imports/components/mojo.ucf:4]
INFO: [Designutils 20-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
[Mon Dec 12 08:30:39 2022] Launched impl_1...
Run output will be captured here: /home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.runs/impl_1/runme.log
# wait_on_run impl_1
[Mon Dec 12 08:30:39 2022] Waiting for impl_1 to finish...
*** Running ngdbuild
with args -intstyle ise -p xc6slx9tqg144-2 -dd _ngo -uc mojo_top_0.ucf mojo_top_0.edf
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -p xc6slx9tqg144-2 -dd _ngo -uc mojo_top_0.ucf mojo_top_0.edf
Executing edif2ngd -quiet "mojo_top_0.edf" "_ngo/mojo_top_0.ngo"
Release 14.7 - edif2ngd P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading NGO file
"/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testpro
ject/testproject.runs/impl_1/_ngo/mojo_top_0.ngo" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "mojo_top_0.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "mojo_top_0.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 1 sec
Writing NGDBUILD log file "mojo_top_0.bld"...
NGDBUILD done.
*** Running map
with args -intstyle pa -w -pr b -mt on mojo_top_0.ngd
Using target part "6slx9tqg144-2".
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal spi_channel[3] connected to top level port
spi_channel(3) has been removed.
WARNING:MapLib:701 - Signal spi_channel[2] connected to top level port
spi_channel(2) has been removed.
WARNING:MapLib:701 - Signal spi_channel[1] connected to top level port
spi_channel(1) has been removed.
WARNING:MapLib:701 - Signal spi_channel[0] connected to top level port
spi_channel(0) has been removed.
WARNING:MapLib:701 - Signal spi_miso connected to top level port spi_miso has
been removed.
WARNING:MapLib:701 - Signal avr_rx connected to top level port avr_rx has been
removed.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 2 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:9a91ad7f) REAL time: 2 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:9a91ad7f) REAL time: 2 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:9a91ad7f) REAL time: 2 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:9a91ad7f) REAL time: 2 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 9.8 Global Placement
Phase 9.8 Global Placement (Checksum:9a91ad7f) REAL time: 3 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 3 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:9a91ad7f) REAL time: 3 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 3 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:9a91ad7f) REAL time: 3 secs
Total REAL time to Placer completion: 3 secs
Total CPU time to Placer completion: 2 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 6
Slice Logic Utilization:
Number of Slice Registers: 0 out of 11,440 0%
Number of Slice LUTs: 0 out of 5,720 0%
Slice Logic Distribution:
Number of occupied Slices: 0 out of 1,430 0%
Number of MUXCYs used: 0 out of 2,860 0%
Number of LUT Flip Flop pairs used: 0
IO Utilization:
Number of bonded IOBs: 16 out of 102 15%
Number of LOCed IOBs: 16 out of 16 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 0 out of 16 0%
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 0.00
Peak Memory Usage: 730 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion (all processors): 3 secs
Mapping completed.
See MAP report file "mojo_top_0.mrp" for details.
*** Running par
with args -intstyle pa mojo_top_0.ncd -w mojo_top_0_routed.ncd -mt on
Constraints file: mojo_top_0.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"mojo_top_0" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 0 out of 11,440 0%
Number of Slice LUTs: 0 out of 5,720 0%
Slice Logic Distribution:
Number of occupied Slices: 0 out of 1,430 0%
Number of MUXCYs used: 0 out of 2,860 0%
Number of LUT Flip Flop pairs used: 0
IO Utilization:
Number of bonded IOBs: 16 out of 102 15%
Number of LOCed IOBs: 16 out of 16 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 0 out of 16 0%
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): Standard
Router effort level (-rl): High
WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.
Starting initial Timing Analysis. REAL time: 2 secs
Finished initial Timing Analysis. REAL time: 2 secs
WARNING:Par:288 - The signal spi_sck_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal avr_rx_busy_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spi_mosi_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spi_ss_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal avr_tx_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal rst_n_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cclk_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 8 unrouted; REAL time: 2 secs
Phase 2 : 8 unrouted; REAL time: 2 secs
Phase 3 : 0 unrouted; REAL time: 3 secs
Phase 4 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Updating file: mojo_top_0_routed.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion: 3 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 594 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 11
Number of info messages: 2
Writing design to file mojo_top_0_routed.ncd
PAR done!
*** Running trce
with args -intstyle ise -o mojo_top_0.twr -v 30 -l 30 mojo_top_0_routed.ncd mojo_top_0.pcf
Loading device for application Rf_Device from file '6slx9.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"mojo_top_0" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Analysis completed Mon Dec 12 08:30:54 2022
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Total time: 1 secs
*** Running xdl
with args -secure -ncd2xdl -nopips mojo_top_0_routed.ncd mojo_top_0_routed.xdl
Release 14.7 - xdl P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"mojo_top_0" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Successfully converted design 'mojo_top_0_routed.ncd' to 'mojo_top_0_routed.xdl'.
[Mon Dec 12 08:30:56 2022] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 342.168 ; gain = 8.000
# launch_runs impl_1 -to_step Bitgen
[Mon Dec 12 08:30:56 2022] Launched impl_1...
Run output will be captured here: /home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testproject/testproject.runs/impl_1/runme.log
# wait_on_run impl_1
[Mon Dec 12 08:30:56 2022] Waiting for impl_1 to finish...
*** Running ngdbuild
with args -intstyle ise -p xc6slx9tqg144-2 -dd _ngo -uc mojo_top_0.ucf mojo_top_0.edf
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -p xc6slx9tqg144-2 -dd _ngo -uc mojo_top_0.ucf mojo_top_0.edf
Executing edif2ngd -quiet "mojo_top_0.edf" "_ngo/mojo_top_0.ngo"
Release 14.7 - edif2ngd P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading NGO file
"/home/justin/Documents/_local/_temp/mojotest/testproject/work/planAhead/testpro
ject/testproject.runs/impl_1/_ngo/mojo_top_0.ngo" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "mojo_top_0.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "mojo_top_0.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 1 sec
Writing NGDBUILD log file "mojo_top_0.bld"...
NGDBUILD done.
*** Running map
with args -intstyle pa -w -pr b -mt on mojo_top_0.ngd
Using target part "6slx9tqg144-2".
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal spi_channel[3] connected to top level port
spi_channel(3) has been removed.
WARNING:MapLib:701 - Signal spi_channel[2] connected to top level port
spi_channel(2) has been removed.
WARNING:MapLib:701 - Signal spi_channel[1] connected to top level port
spi_channel(1) has been removed.
WARNING:MapLib:701 - Signal spi_channel[0] connected to top level port
spi_channel(0) has been removed.
WARNING:MapLib:701 - Signal spi_miso connected to top level port spi_miso has
been removed.
WARNING:MapLib:701 - Signal avr_rx connected to top level port avr_rx has been
removed.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 2 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:9a91ad7f) REAL time: 2 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:9a91ad7f) REAL time: 2 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:9a91ad7f) REAL time: 2 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:9a91ad7f) REAL time: 2 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 2 secs
Phase 9.8 Global Placement
Phase 9.8 Global Placement (Checksum:9a91ad7f) REAL time: 3 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 3 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:9a91ad7f) REAL time: 3 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:9a91ad7f) REAL time: 3 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:9a91ad7f) REAL time: 3 secs
Total REAL time to Placer completion: 3 secs
Total CPU time to Placer completion: 2 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 6
Slice Logic Utilization:
Number of Slice Registers: 0 out of 11,440 0%
Number of Slice LUTs: 0 out of 5,720 0%
Slice Logic Distribution:
Number of occupied Slices: 0 out of 1,430 0%
Number of MUXCYs used: 0 out of 2,860 0%
Number of LUT Flip Flop pairs used: 0
IO Utilization:
Number of bonded IOBs: 16 out of 102 15%
Number of LOCed IOBs: 16 out of 16 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 0 out of 16 0%
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 0.00
Peak Memory Usage: 730 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion (all processors): 3 secs
Mapping completed.
See MAP report file "mojo_top_0.mrp" for details.
*** Running par
with args -intstyle pa mojo_top_0.ncd -w mojo_top_0_routed.ncd -mt on
Constraints file: mojo_top_0.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"mojo_top_0" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 0 out of 11,440 0%
Number of Slice LUTs: 0 out of 5,720 0%
Slice Logic Distribution:
Number of occupied Slices: 0 out of 1,430 0%
Number of MUXCYs used: 0 out of 2,860 0%
Number of LUT Flip Flop pairs used: 0
IO Utilization:
Number of bonded IOBs: 16 out of 102 15%
Number of LOCed IOBs: 16 out of 16 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 0 out of 16 0%
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): Standard
Router effort level (-rl): High
WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.
Starting initial Timing Analysis. REAL time: 2 secs
Finished initial Timing Analysis. REAL time: 2 secs
WARNING:Par:288 - The signal spi_sck_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal avr_rx_busy_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spi_mosi_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spi_ss_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal avr_tx_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal rst_n_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cclk_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 8 unrouted; REAL time: 2 secs
Phase 2 : 8 unrouted; REAL time: 2 secs
Phase 3 : 0 unrouted; REAL time: 3 secs
Phase 4 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Updating file: mojo_top_0_routed.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion: 3 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 594 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 11
Number of info messages: 2
Writing design to file mojo_top_0_routed.ncd
PAR done!
*** Running trce
with args -intstyle ise -o mojo_top_0.twr -v 30 -l 30 mojo_top_0_routed.ncd mojo_top_0.pcf
Loading device for application Rf_Device from file '6slx9.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"mojo_top_0" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Analysis completed Mon Dec 12 08:30:54 2022
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Total time: 1 secs
*** Running xdl
with args -secure -ncd2xdl -nopips mojo_top_0_routed.ncd mojo_top_0_routed.xdl
Release 14.7 - xdl P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"mojo_top_0" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Successfully converted design 'mojo_top_0_routed.ncd' to 'mojo_top_0_routed.xdl'.
*** Running bitgen
with args mojo_top_0_routed.ncd mojo_top_0.bit mojo_top_0.pcf -g Binary:Yes -g Compress -w -intstyle pa
[Mon Dec 12 08:30:59 2022] impl_1 finished
INFO: [Common 17-206] Exiting PlanAhead at Mon Dec 12 08:30:59 2022...
INFO: [Common 17-83] Releasing license: PlanAhead
Finished building project.
Tutorial and description on initial top level Verilog program here.
Others
projects/electronics/fpga/xilinx.txt · Last modified: 15 months ago ( 5 September 2023) by Justin